In semiconductor devices, input receivers are widely used to receive input signals from outside of the semiconductor devices. With recent increases in the operation speed of semiconductor devices, there is a need to increase the sensing speed of input receivers. In the field of memory devices, as the data transfer speed becomes faster, a double data rate (DDR) semiconductor memory device has been developed. The DDR semiconductor memory device employs a rising edge and a falling edge of a clock signal to process data so as to increase the operation speed of memory devices.
FIG. 1 is a circuit diagram illustrating an input receiver 10 used in a DDR semiconductor memory device. Referring to FIG. 1, the input receiver 10 comprises a pre-amplifier 12, a sense amplifier 14, and a latch circuit 16. Pre-amplifier 12 amplifies an input signal IN, from outside of the memory device, with reference to a reference voltage VREF. The pre-amplifier 12 typically comprises a differential pair of PMOS transistors for receiving input signals. Sense amplifier 14 generates an amplified output signal OUT1 and an inverted output signal OUT2 of the pre-amplifier 12 in response to a rising edge of a clock signal CLK (not shown). Latch circuit 16 latches output signal OUT3 and an inverted output signal OUT4 of the sense amplifier 14 so as to generate an output signal OUT and an inverted final output signal OUTB to other circuits in the DDR semiconductor memory device.
Nowadays, DDR semiconductor memory devices are divided into three types: DDR1, DDR2, and DDR3, with maximum operating frequencies of 400 MHz, 800 MHz, and 1.6 GHz, respectively. As the operation frequency of memory devices increase from generation to generation, the prior art input receiver cannot respond immediately, and a waveform distortion results. Furthermore, the input common-mode range of the prior art input receiver is limited and the output common-mode range of the pre-amplifier varies in response to the voltage level of the reference voltage VREF, which affects the performance of the succeeding amplifier stage.
Therefore, there is a need to provide an improved input receiver with an increased input common mode range for high speed applications.